Central processing unit

The Raspberry Pi Zero Wireless Adds Wi-Fi and Bluetooth to the Zero, Costs $10

The Raspberry Pi Zero is a fantastic, miniature version of the Raspberry Pi that shrinks the board down to about the size of a stick of gum, but one problem with it is the lack of wireless features. The Raspberry Pi Zero is a new version that packs in Bluetooth and Wi-Fi for double the price of the original Zero.

The Raspberry Pi Zero Wireless comes with most of the same specs as the standard Pi Zero, but adds in the same 802.11n Wireless LAN and Bluetooth that the Raspberry Pi 3 has. The CPU and RAM are the same as the standard Pi Zero, which are essentially the same as the earliest Raspberry Pi 1 models. Here’s a breakdown of the full specs on the Raspberry Pi Zero…

When Is a CPU’s Cache Flushed Back to Main Memory?

If you are just starting to learn how multi-core CPUs, caching, cache coherency, and memory works, it may seem a little bit confusing at first. With that in mind, today’s SuperUser Q&A post has answers to a curious reader’s question.

Today’s Question & Answer session comes to us courtesy of SuperUser—a subdivision of Stack Exchange, a community-driven grouping of Q&A web sites.

SuperUser reader CarmeloS wants to know when a CPU’s cache is flushed back to main memory:

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time? If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?

When is a CPU’s cache flushed back to main memory?

The Answer

SuperUser contributors David Schwartz, sleske, and Kimberly W have the answer for us. First up, David Schwartz:

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time?

Yes, performance would be terrible if this was not the case. Consider two threads running the same code. You want that code in both L1 caches.

If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?